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AMD announces 128-bit (GPU-oriented?) SSE5 extensions to x86 | |
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| Time: 20:47 EST/01:47 GMT | News Source: Ars Technica | Posted By: Jonathan Tigner | ||
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AMD is looking to repeat the market-leading success they had with x86-64 by introducing another major change to the venerable x86 ISA: a three-operand instruction format for vector instructions in the form of the newly announced "SSE5" extensions. SSE5, which is thoroughly described in the new documentation [PDF] that AMD has released, will be a set of x86 SIMD extensions that's finally comparable to AltiVec in that it eliminates the drawbacks associated with the x86's two-operand limitations which I described a long time ago here. This three-operand format is one of a number of enhancements, some of which seem to be geared toward turning x86 into an ISA that's worthy of use in a GPU. In this respect, SSE5 seems to be what AMD was getting at when they talked about GPU-oriented ISA extensions at the beginning of this year. | ||
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