AMD announces 128-bit (GPU-oriented?) SSE5 extensions to x86

AMD is looking to repeat the market-leading success they had with x86-64 by introducing another major change to the venerable x86 ISA: a three-operand instruction format for vector instructions in the form of the newly announced "SSE5" extensions.

SSE5, which is thoroughly described in the new documentation [PDF] that AMD has released, will be a set of x86 SIMD extensions that's finally comparable to AltiVec in that it eliminates the drawbacks associated with the x86's two-operand limitations which I described a long time ago here.

This three-operand format is one of a number of enhancements, some of which seem to be geared toward turning x86 into an ISA that is worthy of use in a GPU. In this respect, SSE5 seems to be what AMD was getting at when they talked about GPU-oriented ISA extensions at the beginning of this year.

SEE5 also features new instructions for fused multiply-accumulate, integer multiply-accumulate, compare and test, permutation and conditional move, and precision control, rounding, and conversion. Some of these new instructions work with a new 16-bit floating-point format that SSE5 introduces. This "half-precision" floating-point format is popular in GPUs, so this format and its related instructions are likely intended for AMD's forthcoming "Fusion" product.

All told, SSE5 adds over 100 new instructions (base instructions plus variants) to the x86 ISA. No doubt AMD hopes to repeat history here—x86-64 history, not 3DNow! history—by getting Intel to eventually adopt the extensions. However, my (still fairly preliminary) reading of Intel's QuickAssist technology suggests that Intel will take a different approach to integrating many-core, GPU-style acceleration with the x86 ISA. More on this at a later time, though.

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The fact that SSE5 still wil not bring a complete SSE4 implementation to AMD's processors may pose a problem, because it will pit AMD's extensions directly against Intel's. (See the nice Venn diagram in this thread for more.) x86-64 worked because it was a superset of x86, and not a competitor; positioning SSE5 against SSE4 and whatever Intel cooks up next may end up being a recipe for obscurity.

Both "Fusion" and SSE5 are supposed to make their debut in 2009, the latter with AMD's "Bulldozer" core. Not much is known about Bulldozer's microarchitecture, but insofar as it's supposed to be the general-purpose processor core building block in a "modular" approach to integration that sees AMD mixing and matching cores and blocks of different types on a single chip, it will be a direct competitor to Intel's Nehalem.

Three-operand instructions

In a nutshell, a third operand lets a programmer or compiler specify a filter/mod register that can affect the way that a vector operation is carried out on the operands in the other two registers. Such operands are extremely useful for doing in a single instruction a variety of operations that would normally take a sequence of multiple instructions. The use of a third operand register can significantly increase performance for some types of codes, especially in hand-tuned code.

AMD implements this third operand by adding a third opcode byte to instruction and using a new prefix, the DREX prefix, to indicate the use of the new operand format. The DREX prefix replaces the REX prefix introduced with x86-64, and it also can be used to designate one of the three source operands as a destination register, giving a bit more flexibility to programmers and compilers.

Purists will want to know that "three-operand" means "three-register" here, so SSE5 won't be quite up to par with the four-register AltiVec ISA in the flexibility category. SSE's "four-operand" instructions look like OP dest, src1, src2, src3, but dest must equal either src1 or src3 (as specified in the DREX prefix). So one of the operand values in your three source registers still gets replaced with a result, a fact that AltiVec purists are not going to like.